Thread regarding Intel Corp. layoffs

Intel’s fab acceleration plan is a joke

Lots of good questions raised here:

https://semiwiki.com/semiconductor-services/semiconductor-advisors/304429-intel-super-moores-law-time-warp-tsmc-inside-gpu-global-flounders-ipo/

by
| 1990 views | | 6 replies (last ) | Reply
Post ID: @OP+1dAzWC6F

6 replies (most recent on top)

While other paying cr-p. Pat is paying handsomely why would anyone work under him?

by
| | Reply
Post ID: @3rpb+1dAzWC6F

Renaming the process nodes to make them sound more advanced may help the image in the media. However, real customers who are paying millions to commit to a fab will be scrutinizing the technology with a very fine tooth comb. It's not just the density but the PDK, proven IP portfolio, support, pricing, roadmap, partners, EDA compatibility, reliability and trust, yield, and of course PPA. Intel fab 1.0 was a complete disaster in all these metrics. Pat now wants to the world to believe that he will close the gap on everything while simultaneously catching up to TSMC. Let's ask the big question Pat. What has changed besides swapping out the CEO ? The world understands that the CEO is still stuck in a massive machine with ton of worthless VP's and managers who only care about defending their turf and paycheck. Top technical talent are locked up at Apple, Nvidia, AMD, QCOM, FB, GOOG, etc. None of them are leaving these companies to go to a sinking ship because they don't have millions in stock options like the CEO. They don't have the upside like Pat.

by
| | Reply
Post ID: @2zow+1dAzWC6F

Intel is a joke. Period.

by
| | Reply
Post ID: @1spe+1dAzWC6F

From the article:

“What we don’t see is how Intel will have an advantage. Its not like ASML will sell its High NA tools only to Intel and forsake its biggest and bestest customer TSMC. Thats not gonna happen.

Intel has also not gone through all the pain and learning process of EUV and has a miniscule amount of experience in real world use as compared to TSMC years of experience running many, many wafers. on EUV tools.

Much of the EUV learning that Intel has yet to do is a prerequisite for figuring out High NA.

Its quite clear that with all the experience gained in its huge lead in EUV that TSMC will enter High NA EUV with an advantage over Intel and not the other way around.”

by
| | Reply
Post ID: @1gmt+1dAzWC6F

The Moore Pat talks up his delusions of regaining the lead and acceleration even faster the Moore the world laughs at his leadership.

Be happy you left or be so sad this is your CEO, better a clown, a bean counter or a fanatic, sadly all three part of the three stooges leading Intel into the abyss and most certainly a round of layoffs after a binge of hiring.

https://www.taiwannews.com.tw/en/news/4327937

by
| | Reply
Post ID: @1jci+1dAzWC6F

Yes. Intel will need to rely on metaphysics and not physics to pull off Pat's pipe-dreams!

by
| | Reply
Post ID: @ugd+1dAzWC6F

Post a reply

: