Thread regarding Intel Corp. layoffs

Intel @ JPM Global Tech Conf (Excerpt)

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Murthy Renduchintala:

...I think that silicon leadership is really important in as much as it supports product leadership. Silicon leadership in and of itself is only one of the aspects required. First of all Intel is a product company, it's not necessarily focused on being a merchant foundry. And in addition to silicon leadership, you really also need right architectural capability, the ability to execute silicon programs to predictable timelines, and you need an arsenal of capabilities and packaging, assembly and test technologies. So bringing all of those the weather is really what drives product leadership.

In terms of 10-nanometer, we are shipping 10-nanometer in low volumes. I think that if you go back to when we originally defined the recipe of 10-nanometer back in early 2014, we defined some very aggressive goals for our second-generation hyper-scaling. We targeted a 2.7x scaling factor, from 14-nanometers which was in the very stages of product ramp at that point in time. And 14-nanometers with in and of itself of 2.4x scaling on 22 nanometers, so clearly our engineering team in TMG had very, very ambitious goals in terms of the transistor scaling required.

That required a lot of innovations to come together and maybe those plans were a little bit more aggressive in hindsight than was ideal. And so, therefore we had a little bit of a greater challenge in bringing 10-nanometer to market than we had originally expected. However, the issues that we faced in getting that to prime time yield and not fundamental. We know what to fix and we’re busy going about fixing that. In the meantime, we found tremendous intra-node capability within our 14-nanometer process.

In fact from the very first generation of our 14-nanometer to the latest generation of 14-nanometer product, we've been able to deliver over 70% performance improvement as a result of those intra-node modifications and desirable changes. And that's quite frankly Harlan has given us the ability to make sure that we get 10-nanometer yields right before we go into mainstream production. And so, therefore we’re comfortable with the 14-nanometer roadmap that will give us leadership products in the next 12 to 18 months, as we seek to optimize the cost structure and yields of our 10-nanometer portfolio.

https://seekingalpha.com/article/4174405-intel-intc-presents-jp-morgan-46th-annual-global-technology-media-communications-conference?part=single

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Post ID: @OP+TbBi4Tp

6 replies (most recent on top)

Who ever drove PTD to do 2.7 is a moron. The sheep in PTD especial the senior fellows all should be fired!

That additional scaling looks pretty good on a ppt foil and appearing to others as you are the leader, little detail where the puck is the product with 2.7 scaling? Oh yeah in you can get that amazing scaling in a entry laptop with all the 2.7 density fused out because it don’t work 😂😂😂😂😂

https://semiaccurate.com/2018/05/21/when-is-intels-10nm-process-scheduled-for/

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Post ID: @8whe+TbBi4Tp

He didn't just admit that the 2.7x shrink Target was too aggressive, did he?

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Post ID: @1tap+TbBi4Tp

10nm after billions spent is shipping without any graphics in an entry laptop, what a joke of leadership.

https://www.anandtech.com/show/12749/first-10nm-cannon-lake-laptop-spotted-online-lenovo-ideapad-330-for-449

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Post ID: @1skt+TbBi4Tp

@ebw- Yes! Making billions in profits. A concept that a troll such as yourself cannot grasp.

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Post ID: @haf+TbBi4Tp

Intel being run Like a Trump company

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Post ID: @ebw+TbBi4Tp

Eye Opener:

And one of the things that the 10-nanometer experience has provided us where there is a eye-opening learning lease within Intel's about how much goodness can be achieved intra-node.

Of course when you work in the TSMC or Samsung or global foundries environment, that’s somewhat taken for granted. But in the Intel regime that’s something that was really-really very eye-opening for us in 14-nanometers.

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Post ID: @tun+TbBi4Tp

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