Are the chip architects appreciative of his leadership or resent him changing things?
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I have never run across any serious chip designer running EDA tools locally on a laptop (or desktop). The only cases I have ever seen are consultants doing low end layout work using cheap or free layout tools for a low end chip project. However, consultants don't COT their own EDA licenses because they can't expense that to the client. Go ahead and call Synopsys, Cadence, or Mentor and say you are an individual who wants to buy one seat of one tool. There will be silence as they try to figure out how to even direct your call.
It has already pointed out that EDA licenses are outrageously expensive so you always need to keep the utilization very high. In order to do that the licenses need to be floating in a cluster so that your US team and offshore team can utilize them around the clock. Nobody puts a few hundred thousand dollars in licenses locked up in a laptop than can't be shared while you are sleeping. Sure, you can just pull a floating license off VPN and run locally on your laptop. However, if you're already on VPN, why the hell would you then run the job locally on your laptop instead of the compute farm you're already connected to ? Also, the memory and compute resources for majority of chip design tasks simply cannot be done on a laptop. Yes, there are a few niche cases, like simulations, that can be done on a laptop. However, that still doesn't solve the issue of not being able to share very expensive licenses. There's also the issue tech files and models that most EDA tools require. These files contains lots of confidential information and nobody wants a local copy on laptop that can be left in the back of an Uber or Starbucks. You also run into the problem of tech file and model coherency. In a very complex project, like CPU design, management of tech file and models versions are critical. You would NEVER fork off a local copy on a laptop. BTW, the coherency issue is so critical that it even applies to the version of the EDA tool. Forking a local version on a laptop is a very bad idea. Finally, there are absolutely no advantages, but tons of disadvantages to running anything locally even if you have a large server farm in your house. With VPN and VNC no serious project would be done this way, even lower end ASICs, and especially not the most complex CPU projects. Broadband connectivity is ubiquitous now. Unless Keller really needs to do some work off grid in a cave in Afghanistan he will be designing chips like everyone else by using a dumb terminal with VPN. However, using mobile workstations are great for architecture, Solidworks, rendering, etc.
Synopsys, not Synoptics, is the word you're looking for. I don't know of anyone who runs any EDA tools from a laptop because there are no advantages to doing so. You might be able to run some light logic sims locally on a laptop but you would still need to be connected to the network to pull a floating FLEXlm license. It would make no sense for any company to purchase a node locked license for a laptop due to inefficient use of EDA spend.
For people with no experience in the chip design field low end EDA licenses, like simulators, are priced from $20K to $50K per seat per year. Higher end sim tools, like fast SPICE, are around $100K per seat per year. Back end tools, like ICC2 or Innovus, go for about $400K to $800K per seat per year depending on the features you want. You can buy a temp license during tape-out crunch, usually for point tools like Calibre but they will charge you about $20K per seat for a few days. Prices will vary and nobody pays list price. Larger companies, and startups, will have better discounts but the prices above will give you some ballpark figures.
Almost anything you do in CPU design, particularly physical design but even front end work, requires high compute and memory resources. However, it's the management of EDA licenses that necessitates running everything on a load sharing compute cluster. I don't doubt that Intel IT purchased Jimmy a nice laptop but that has nothing to do with running EDA tools.
Regarding the OP I have worked with Keller. He has strong opinions. Let's leave it at that.
Actually, I have worked at Intel. If you worked at Intel, I mentioned an intel validation process. I'm clearly capable of articulating. The tools mentioned are used by almost all semiconductor firms and others that use Electronic Design Automation tools.
@1jpz - Not a good sign. Sounds like he's resting and vesting.
@1jpz only when they need to roll him out for the press
He's always WFH. No one ever saw him around.