Qualcomm is not going to gain much in realignment. Things will become worse. All ppl who are good in emailing projecting for the junk work they have done as a NASA project survived.
Give a device and ppl to collect logs with out any help. all junk ppl will go away. more than 50 percent doenst know how to take logs. what they know abt debugging
I'm glad some folks can find the truth in this one. For the rest of us, could you please complete the translation to English.
This is true for all departments. Higher ups have 0% idea what's going on , they don't even have any idea how things are done for commercialization ...they just blabber and talk rubbish to try this or try that without concrete idea.
This layoff will not help at all. It will make life of engineer bad to worse and a**le leads will pressurize more in desperation to save their a.
Wow are u talking about QCT quality group? Yes they are exactly how you described here....poor QCT
New Position:
They have a position open in Irvine, CA:
Engineer, Senior or Principal Electronic Design 503. PHY electrical bench test methodologies and procedures per industry standards - 10GbE (IEEE 802.3ae).They will pay a major six figure base salary plus bonus and full benefits. They will relocate. For more detailed information, forward resumes in word format to al@MWSHire.com and answer the following questions.
• Visa Status:
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In this role you would join Client's Infrastructure Networking Group in developing, characterizing and qualifying high-speed broadband networking devices.
Their products include (1) 10/40/100 Gigabit Ethernet-based transceivers enabling manufacturers to build affordable 10 Gigabit Ethernet-based SFP+ over structured cabling in the data center, (2) Fibre Channel PHY to build fiber channel disk drive arrays, blade servers, and fibre channel storage systems, and (3) 10G SONET/SDH/OTN transceivers for telecommunications and service providers to efficiently deliver data and voice traffic over existing fiber networks.
In this position you will:
Develop comprehensive test plans and test strategies for post-silicon analog electrical parameters of physical layer (PHY) SerDes (Serializer and Deserializer) of high-speed broadband Mix-signal ASICs.
Develop and optimize PHY electrical bench test methodologies and procedures per industry standards - 10GbE (IEEE 802.3ae, IEEE 802.3ak, IEEE 802.3ap, IEEE 802.3aq), 40/100GbE (IEEE 802.3ba, IEEE 802.3bg), and 100GbE (IEEE 802.3bj, IEEE 802.3bm).
Perform post-silicon PHY bench testing of analog electrical parameters of high-speed broadband Mix-signal ASICs.
Lead and train junior engineers.
Generate comprehensive test reports and analysis.
Develop and implement bench test automation.
Collaborate with IC design team on chip performance optimization and failure analysis.
Job Requirement:
EE PhD or MS with minimum 6+ year working experience in high-speed broadband communication post-silicon analog test environment.
Must be an expert in PHY test methodologies specified in at least one of above listed IEEE standards.
This job requirement should focus on physical interface I/O electrical parameter test which is analog in nature and get into RF region with today’s ever higher data rate. We use Keysight DCA-J and J-BERT extensively.
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So true my friends....
So true my friends....
well said